====== MCA banks on AMD Family 17h ======

Specifically, the //Machine Check Control// registers.

===== CPU Core =====

==== LS ====

| **Legacy MSR** | 0x0000_0400 |
| **New MSR** | 0xC000_2000 |

^ Bit ^ Name ^ Description ^
| 20 | %%L2DataErr%% |  |
| 19 | %%DcTagErr5%% |  |
| 18 | %%DcTagErr3%% |  |
| 17 | PDC |  |
| 16 | L2DTLB |  |
| 15 | %%DcTagErr4%% |  |
| 14 | %%DcDataErr3%% |  |
| 13 | %%DcDataErr2%% |  |
| 12 | %%DcDataErr1%% |  |
| 11 | %%DcTagErr2%% |  |
| 10 | %%SystemReadDataErrorT1%% |  |
| 9 | %%SystemReadDataErrorT0%% |  |
| 8 | %%IntErrTyp2%% |  |
| 7 | %%IntErrTyp1%% |  |
| 6 | %%DcTagErr1%% |  |
| 5 | %%DcTagErr6%% |  |
| 3 | L1DTLB |  |
| 2 | MAB |  |
| 1 | STQ |  |
| 0 | LDQ |  |

==== IF ====

| **Legacy MSR** | 0x0000_0404 |
| **New MSR** | 0xC000_2010 |

^ Bit ^ Name ^ Description ^
| 13 | %%SystemReadDataError%% |  |
| 12 | %%L2RespPoison%% |  |
| 11 | %%L2BtbMultiHit%% |  |
| 10 | %%L1BtbMultiHit%% |  |
| 9 | %%BpqSnpParT1%% |  |
| 8 | %%BpqSnpParT0%% |  |
| 7 | %%L2ItlbParity%% |  |
| 6 | %%L1ItlbParity%% |  |
| 5 | %%L0ItlbParity%% |  |
| 4 | %%DqParity%% |  |
| 3 | %%DataParity%% |  |
| 2 | %%TagParity%% |  |
| 1 | %%TagMultiHit%% |  |
| 0 | %%OcUtagParity%% |  |

==== L2 ====

| **Legacy MSR** | 0x0000_0408 |
| **New MSR** | 0xC000_2020 |

^ Bit ^ Name ^ Description ^
| 3 | Hwa |  |
| 2 | Data |  |
| 1 | Tag |  |
| 0 | %%MultiHit%% |  |

==== DE ====

| **Legacy MSR** | 0x0000_040C |
| **New MSR** | 0xC000_2030 |

^ Bit ^ Name ^ Description ^
| 8 | OCBQ |  |
| 7 | %%UcSeq%% |  |
| 6 | %%UcDat%% |  |
| 5 | Faq |  |
| 4 | Idq |  |
| 3 | %%UopQ%% |  |
| 2 | Ibq |  |
| 1 | %%OcDat%% |  |
| 0 | %%OcTag%% |  |

==== Old NBIO ====

| **Legacy MSR** | 0x0000_0410 |

This MCA bank has been disabled in Family 17h.  It returns zeros and ignores writes.

==== EX ====

| **Legacy MSR** | 0x0000_0414 |
| **New MSR** | 0xC000_2050 |

^ Bit ^ Name ^ Description ^
| 10 | BBQ |  |
| 9 | SQ |  |
| 8 | STATQ |  |
| 7 | RETDISP |  |
| 6 | CHKPTQ |  |
| 5 | PLDAL |  |
| 4 | PLDAG |  |
| 3 | IDRF |  |
| 2 | FRF |  |
| 1 | PRF |  |
| 0 | WDT |  |

==== FP ====

| **Legacy MSR** | 0x0000_0418 |
| **New MSR** | 0xC000_2060 |

^ Bit ^ Name ^ Description ^
| 6 | HWA |  |
| 5 | SRF |  |
| 4 | RQ |  |
| 3 | NSQ |  |
| 2 | SCH |  |
| 1 | FL |  |
| 0 | PRF |  |

===== L3 =====

| **Legacy MSR** | 0x0000_04[1C,20,24,28] (CCX0), [2C,30,34,38] (CCX1) |
| **New MSR** | 0xC000_20[7-A]0 (CCX0), [B-E]0 (CCX1) |

^ Bit ^ Name ^ Description ^
| 7 | HWA |  |
| 6 | %%XiVictimQueue%% |  |
| 5 | %%SdpParity%% |  |
| 4 | %%DataArray%% |  |
| 3 | %%MultiHitTag%% |  |
| 2 | Tag |  |
| 1 | %%MultiHitShadowTag%% |  |
| 0 | %%ShadowTag%% |  |

===== Data Fabric =====

==== CS ====

| **Legacy MSR** | 0x0000_0450 (CS0), 454 (CS1) |
| **New MSR** | 0xC000_2140 (CS0), 2150 (CS1) |

^ Bit ^ Name ^ Description ^
| 8 | SPF_ECC_ERR |  |
| 7 | ATM_PAR_ERR |  |
| 6 | SDP_PAR_ERR |  |
| 5 | FTI_PAR_ERR |  |
| 4 | FTI_RSP_NO_MATCH |  |
| 3 | FTI_ILL_RSP |  |
| 2 | FTI_SEC_VIOL |  |
| 1 | FTI_ADDR_VIOL |  |
| 0 | FTI_ILL_REQ |  |

==== PIE ====

| **Legacy MSR** | 0x0000_0458 |
| **New MSR** | 0xC000_2160 |

^ Bit ^ Name ^ Description ^
| 3 | FTI_DAT_STAT |  |
| 2 | GMI |  |
| 1 | CSW |  |
| 0 | HW_ASSERT |  |

===== UMC =====

| **Legacy MSR** | 0x0000_043C (umc0?), (? 0x0000_0440 umc1?) |
| **New MSR** | 0xC000_20F0 (umc0?), (? 0xC000_2100 umc1?) |

^ Bit ^ Name ^ Description ^
| 5 | %%WriteDataCrcErr%% | A write data CRC error on the DRAM data bus |
| 4 | %%AddressCommandParityErr%% |  |
| 3 | %%ApbErr%% |  |
| 2 | %%SdpParityErr%% |  |
| 1 | %%WriteDataPoisonErr%% |  |
| 0 | %%DramEccErr%% | An ECC error on DRAM read |

===== PB =====

| **Legacy MSR** | 0x0000_044C |
| **New MSR** | 0xC000_2130 |

^ Bit ^ Name ^ Description ^
| 0 | %%EccError%% | An error in the Parameter Block RAM array |

===== PSP =====

| **Legacy MSR** | 0x0000_0448 |
| **New MSR** | 0xC000_2120 |

^ Bit ^ Name ^ Description ^
| 0 | %%PspMemoryError%% |  |

===== SMU =====

| **Legacy MSR** | 0x0000_0444 |
| **New MSR** | 0xC000_2110 |

^ Bit ^ Name ^ Description ^
| 0 | %%SmuMemoryError%% |  |