Atheros MIPS platform

The AR71xx/AR91xx/AR933x SoCs are a MIPS24k based CPU core with various peripherals. Here's some of the weirdnesses.

• The AR71xx NIC TX path requires buffers to be aligned on 4 byte address boundaries; all fragments bar the last must be a size of an even multiple of 4 bytes. The if_arge driver got this subtly wrong. This has been filed in PR kern/148307 and I fixed it in a subsequent commit.
• .. I think this was fixed in AR724x and later chips; go test?

• The AR71xx, AR913x and earlier AR724x have both OHCI and EHCI drivers where applicable. The later AR724x and the AR933x SoCs only have EHCI - and then an internal USB hub converts non high-speed devices to high-speed USB 2.0 devices.

• There's apparently a silicon bug with the AR71xx and DMA. Various chipsets, including the AR5213, do not have the workaround. I'm not sure which do and which don't. The fix is to limit the PCI bus transaction size (both TX/RX ? Just RX? I'm not sure!) to a smaller size. (TODO: add link to changeset from imp which includes the workaround.) You should enable 'options AH_RXCFG_SDMAMW_4BYTES' to enable the workaround for the AR5212 era chipsets.

• AR91xx doesn't have a PCI bus.
• The AR91XX DDR registers for forcing writeback (ie, “flush”) overlap with the AR71xx PCI window registers and are thus not in the same place as the AR71XX registers.
• The ethernet MAC address and wifi calibration data needs to be extracted from flash. The Linux code: u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);

ar71xx_set_mac_base(mac);

.. go read the code that calls that and figure out how ethernet MACs are read.