--- sys/i386/i386/in_cksum.c.back	2007-07-17 18:32:52.000000000 +0000
+++ sys/i386/i386/in_cksum.c	2007-07-17 19:07:35.000000000 +0000
@@ -259,7 +259,7 @@
  * load the value into a register but will not use it.  Since modern CPUs
  * reorder operations, this will generally take place in parallel with
  * other calculations.
- */
+ *
 #define ADD(n)	__asm __volatile \
 		("addl %1, %0" : "+r" (sum) : \
 		"g" (((const u_int32_t *)w)[n / 4]))
@@ -270,6 +270,9 @@
 		("" : : "r" (((const u_int32_t *)w)[n / 4]))
 #define MOP	__asm __volatile \
 		("adcl         $0, %0" : "+r" (sum))
+ * remove those macros because gcc will insert add instructions 
+ * between __asm expressions
+ */
 
 u_short
 in_cksum_skip(m, len, skip)
@@ -341,15 +344,25 @@
 		 * Advance to a 486 cache line boundary.
 		 */
 		if (4 & (int) w && mlen >= 4) {
-			ADD(0);
-			MOP;
+		/*	ADD(0);
+			MOP;*/
+		  	__asm volatile ("addl %1, %0 \n"
+					"adcl $0, %0"
+	 				: "+r" (sum) 
+					: "g" (((const unsigned int *)w)[0 / 4]));
 			w += 2;
 			mlen -= 4;
 		}
 		if (8 & (int) w && mlen >= 8) {
-			ADD(0);
+		/*	ADD(0);
 			ADDC(4);
-			MOP;
+			MOP;*/
+			__asm volatile ("addl %1, %0 \n"
+					"adcl %2, %0 \n"
+					"adcl $0, %0"
+   					: "+r" (sum) : 
+					"g" (((const unsigned int *)w)[0 / 4]),
+   					"g" (((const unsigned int *)w)[4 / 4]));
 			w += 4;
 			mlen -= 8;
 		}
@@ -379,7 +392,7 @@
 			 * is initially 33 (not 32) to guaranteed that
 			 * the LOAD(32) is within bounds.
 			 */
-			ADD(16);
+			/* ADD(16);
 			ADDC(0);
 			ADDC(4);
 			ADDC(8);
@@ -388,12 +401,30 @@
 			ADDC(20);
 			ADDC(24);
 			ADDC(28);
-			MOP;
+			MOP; */
+			__asm volatile ("addl %1, %0 \n"
+					"adcl %2, %0 \n"
+					"adcl %3, %0 \n"
+					"adcl %4, %0 \n"
+					"adcl %5, %0 \n"
+					"adcl %7, %0 \n"
+					"adcl %8, %0 \n"
+					"adcl %9, %0 \n"
+					"adcl $0, %0" : "+r" (sum) :
+					"g" (((const unsigned int *)w)[16 / 4]),
+					"g" (((const unsigned int *)w)[0 / 4]),
+					"g" (((const unsigned int *)w)[4 / 4]),
+					"g" (((const unsigned int *)w)[8 / 4]),
+					"g" (((const unsigned int *)w)[12 / 4]),
+					"r" (((const unsigned int *)w)[32 / 4]),
+					"g" (((const unsigned int *)w)[20 / 4]),
+					"g" (((const unsigned int *)w)[24 / 4]),
+					"g" (((const unsigned int *)w)[28 / 4]));
 			w += 16;
 		}
 		mlen += 32 + 1;
 		if (mlen >= 32) {
-			ADD(16);
+			/* ADD(16);
 			ADDC(0);
 			ADDC(4);
 			ADDC(8);
@@ -401,23 +432,54 @@
 			ADDC(20);
 			ADDC(24);
 			ADDC(28);
-			MOP;
+			MOP;*/
+			__asm volatile ("addl %1, %0 \n"
+					"adcl %2, %0 \n"
+					"adcl %3, %0 \n"
+					"adcl %4, %0 \n"
+					"adcl %5, %0 \n"
+					"adcl %6, %0 \n"
+					"adcl %7, %0 \n"
+					"adcl %8, %0 \n"
+					"adcl $0, %0" : "+r" (sum) :
+					"g" (((const unsigned int *)w)[16 / 4]),
+					"g" (((const unsigned int *)w)[0 / 4]),
+					"g" (((const unsigned int *)w)[4 / 4]),
+					"g" (((const unsigned int *)w)[8 / 4]),
+					"g" (((const unsigned int *)w)[12 / 4]),
+					"g" (((const unsigned int *)w)[20 / 4]),
+					"g" (((const unsigned int *)w)[24 / 4]),
+					"g" (((const unsigned int *)w)[28 / 4]));
 			w += 16;
 			mlen -= 32;
 		}
 		if (mlen >= 16) {
-			ADD(0);
+			/* ADD(0);
 			ADDC(4);
 			ADDC(8);
 			ADDC(12);
-			MOP;
+			MOP;*/
+			__asm volatile ("addl %1, %0 \n"
+					"adcl %2, %0 \n"
+					"adcl %3, %0 \n"
+					"adcl %4, %0 \n"
+					"adcl $0, %0": "+r"(sum): 
+					"g" (((const unsigned int *)w)[0 / 4]),
+					"g" (((const unsigned int *)w)[4 / 4]),
+					"g" (((const unsigned int *)w)[8 / 4]),
+					"g" (((const unsigned int *)w)[12 / 4]));
 			w += 8;
 			mlen -= 16;
 		}
 		if (mlen >= 8) {
-			ADD(0);
+			/* ADD(0);
 			ADDC(4);
-			MOP;
+			MOP;*/
+			__asm volatile ("addl %1, %0 \n"
+					"adcl %2, %0 \n"
+					"adcl $0, %0": "+r"(sum): 
+					"g" (((const unsigned int *)w)[0 / 4]),
+					"g" (((const unsigned int *)w)[4 / 4]));
 			w += 4;
 			mlen -= 8;
 		}