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| alancox:pmapreview [2021/07/05 06:08] – AlanCox | alancox:pmapreview [2022/09/06 08:37] (current) – AndrewTurner |
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| * Eliminate unnecessary I/D-Cache coherence operations. | * Eliminate unnecessary I/D-Cache coherence operations. |
| * //On a machine with a PIPT L1 I-cache, I tried reenabling selective "ic" operations in arm64_icache_flush_range() (rather than flushing the entire I-cache), but performance got slightly worse.// | * //On a machine with a PIPT L1 I-cache, I tried reenabling selective "ic" operations in arm64_icache_flush_range() (rather than flushing the entire I-cache), but performance got slightly worse.// |
| * BUG: pmap_enter_l2() is often used to map code superpages. However, we do not currently call arm64_icache_flush_range(). | * <del>BUG: pmap_enter_l2() is often used to map code superpages. However, we do not currently call arm64_icache_flush_range().</del> https://reviews.freebsd.org/D31181 |
| * These coherence operations can be disabled on some newer cores, //e.g.//, Graviton 2, which implement coherence in hardware. Use an IFUNC? | * <del>These coherence operations can be disabled on some newer cores, //e.g.//, Graviton 2, which implement coherence in hardware.</del> Use an IFUNC? |
| * //On these cores, the "ic" instruction never broadcasts an invalidation, so most of the overhead is automatically eliminated.// | * //On these cores, the "ic" instruction never broadcasts an invalidation, so most of the overhead is automatically eliminated.// |
| * <del>Implement access bit emulation.</del> | * <del>Implement access bit emulation.</del> |
| * pmap_enter() need not perform a TLB invalidation on a wiring change. In places like pmap_enter() or pmap_remove(), we don't need to invalidate the TLB if ATTR_AF is clear. | * pmap_enter() need not perform a TLB invalidation on a wiring change. In places like pmap_enter() or pmap_remove(), we don't need to invalidate the TLB if ATTR_AF is clear. |
| * pmap_invalidate_range() should flush the entire TLB if the range exceeds a threshold. | * pmap_invalidate_range() should flush the entire TLB if the range exceeds a threshold. |
| * With TLBI you can choose whether "page walk cache" entries are flushed. So, operations, like pmap_protect(), that do not deallocate l2 or l3 tables could use a variant of pmap_invalidate_range() that only invalidates leaf-level entries. | * <del>With TLBI you can choose whether "page walk cache" entries are flushed. So, operations, like pmap_protect(), that do not deallocate l2 or l3 tables could use a variant of pmap_invalidate_range() that only invalidates leaf-level entries.</del> **4ccd6c137f5b** |
| * <del>Given that the TLBI "is" variants broadcast the invalidation to other cores, I don't see why we are pinning to a core at the start of pmap_invalidate_*().</del> **r355145** | * <del>Given that the TLBI "is" variants broadcast the invalidation to other cores, I don't see why we are pinning to a core at the start of pmap_invalidate_*().</del> **r355145** |
| * <del>BUG: Preemption after an "ic" or "tlbi" instruction but before a "dsb" instruction by the same processor is problematic.</del> **r355427** | * <del>BUG: Preemption after an "ic" or "tlbi" instruction but before a "dsb" instruction by the same processor is problematic.</del> **r355427** |
| * <del>Change vmspace0's pmap to use a zeroed physical page as the root of the ttbr0 page table. Currently, it inherits an identity mapping from locore.S. https://reviews.freebsd.org/D22606</del> | * <del>Change vmspace0's pmap to use a zeroed physical page as the root of the ttbr0 page table. Currently, it inherits an identity mapping from locore.S. https://reviews.freebsd.org/D22606</del> |
| * Port r352874 from amd64: Defer freeing of PV chunk pages in pmap_remove_pages() until after the last PV list lock is released. | * Port r352874 from amd64: Defer freeing of PV chunk pages in pmap_remove_pages() until after the last PV list lock is released. |
| | * **[In progress: andrew]** |
| | * <del>Use the ttbr %%CnP%% flag</del> |
| | * <del>**[In progress: andrew]** Not seeing any performance improvements in current (2021) hardware</del> |
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