Hardware Overview

This is an old revision of the document!

The Atheros 802.11 NIC is, at it's core, a DMA engine with hardware timers implementing the 802.11 packet timing. The hardware handles doing the OFDM/CCK RF encoding and decoding.

The NIC can be broken down into a few larger blocks:

The MAC - implements the 802.11 packet timing, encryption/decryption, packet scheduling, DMA and queuing
The PHY - implements the 802.11 packet encoding and decoding.
The radio (analog) - implements the 2.4GHz / 5GHz radio.
Power control / RTC - handling turning on and off power and clock generation to various parts of the device
Host interface - the glue between the internal AHB and whatever the host supports - PCI, PCIe, etc

There's more going on internally. (TODO: go dumpster diving through the Atheros patents to look for hardware descriptions.)

The MAC side is further broken down into:

PCU - packet control unit. This handles handles packet reception.
QCU - queue control unit. This handles packet transmission DMA.
DCU - (?) control unit. This handles the 802.11 side of packet transmission - contention window management, QoS settings, etc.
FIFOs - there's a TX and an RX FIFO.

The MAC itself implements (not an exhaustive list!):

contention window and backoff timers
RTS generation, CTS-to-self generation, CTS response
ACK response
Block-ACK response on 802.11n hardware
Beacon generation
On later chips, it supports waking up the hardware when it sees various things - WoW packets, TIM bit set for itself, etc
Transmit and receive DMA
Interrupt generation
MIB counters - TX frame, RX frame, RX clear, cycle timers

== PHY ===

The PHY implements the packet encoding and decoding. The MAC selects packets to send to the PHY for transmission; the PHY decodes packets from the air and sends them to the MAC for reception. (Yes, the Atheros NIC drivers do no actual packet encoding/decoding in software - the hardware does all of this. It's not a software defined radio.)

It is also responsible for watching the air and determining when the air is clear enough to transmit. The MAC has an input (RX_CLEAR) which it uses to determine whether it's able to transmit or not.

The PHY has one (or more, for later chips) ADCs and DACs which handle receiving and transmitting encoding frames to the analog section.

== Analog ===

The Analog section links into the PHY via the ADCs and DACs. It's responsible for tuning to the relevant 2 or 5GHz frequency and converting things as needed.

== Chipset specifics ===