NetFPGA SUME reference NIC device driver

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Student: Denis Salopek (denis.sale@gmail.com)
Mentors: Marko Zec, Bjoern A. Zeeb (zec@fer.hr, bz@freebsd.org)

Project description

NetFPGA is an open-source project aimed to foster networking hardware prototyping. Their latest and de-facto standard development board is NetFPGA SUME with a Virtex-7 FPGA and 4 SFP+ (10 Gbps) ports. The board’s open-source repository includes 14 designs: 'reference' projects to be used as a first step to building customized NICs, switches, routers, etc., as well as community member contributed projects. The NetFPGA software ecosystem, including the device drivers, is unfortunately Linux-centric, with no support for FreeBSD.

This project will enable using NetFPGA SUME as a 4×10 Gbps NIC on hosts running FreeBSD. There are already FreeBSD drivers for older (now obsolete) versions of NetFPGA 10G (if_nf10bmac(4)) and NetFPGA 1G (https://github.com/wkoszek/freebsd_netfpga), both incompatible with the SUME board but could provide some valuable insight. Writing a device driver on top of the iflib(9) framework should inherently provide support for netmap(4), which would enable high-speed traffic exchange between (custom) NetFPGA designs and userspace network applications, paving the way for experimentation with new hardware / software network processing paradigms.

Modified ng_eiface(4) module as a mockup driver / iflib(9) playground
NetFPGA SUME driver skeleton with basic PIO register communication
NetFPGA SUME reference NIC device driver for FreeBSD with basic NIC functionalities (sending/receiving packets via DMA)
netmap(4) integration with the developed device driver

June 1st: Start of coding
- Develop a mockup driver based on ng_eiface(4) and iflib(9). Start writing a generic driver for basic communication between the OS and NetFPGA, mostly to learn more about the process of kernel driver programming and inner workings of host-NetFPGA communication (device interrupts, PCIe PIO and DMA). This will serve as a base for the next step. Improve the driver communication with FPGA registers, enable reading/writing to/from specific memory locations, gain control over DMA transfers. The mockup driver is fully functional and NetFPGA register communication is enabled.
July 3rd: Mid-term Evaluations #1
- Merge the previously made separate mockup iflib(9) and NetFPGA generic drivers to enable sending/receiving network packets to/from NetFPGA/OS. Implement interrupt handlers.
July 31st: Mid-term Evaluations #2
- Testing with different Netmap applications (for sending/receiving traffic). This will almost certainly reveal bugs in the driver so fixing them will inevitably take away some time. Driver optimizations for better traffic throughput. Last minute minor fixes and finishing touches. Documentation finishing up.
August 31st: Final Evaluations