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This page contains my ideas on how to design and implement a framework for configuring (embedded) ethernet switch controllers from FreeBSD.
Many wireless router devices contain multiple Ethernet ports that are implemented by an Ethernet switch chip. These chips can often be configured in varioous ways. Interesting aspects include the port link paramters, VLAN settings, per-port and per-switch statistics. Newer switch chips contain hardware features for NAT, PPPoE processing, and similar advanced features.
Design Goals
The framework should:
- Allow an administrator to configure common aspects of the switch
- The administration interface should be generic (not switch model specific)
- Allow switch model specific configuration extensions
Abstract Switch
In order to have a generic configuration interface, the framework has the concept of an abstract switch that models the various features and configuration settings of the concrete switch chips. This abstract switch has these features:
- 2 to 32 physical ports, some of which might be internal to the device (CPU attachment)
- external ports can have PHYs for link control
- port-based VLAN support
- .1q VLAN support with a limited number of VLANs (including tagged/untagged ports)
- .1q VLAN support with all possible VID values
- .1q Priority support and frame classification
Open Issues
The following questions likely should be answered:
- How are statistics going to be exposed? sysctl, SNMP/MIB framework, userland utility? How are the various counters offered and discovered, since the switch controllers differ widely in this aspect?
- How can more advanced aspects be modeled in a generic way, how would other system componentes (natd, etc.) tie into these?
- Many of these controllers allow the CPU to control spanning tree functions; can we reuse the STP code from if_bridge?
Switch Controllers
RTL8366RB
This Realtek Ethernet switch is used in the TP-LINK TL-WR1043ND. It has five ports with built-in PHYs and one MII port for connection to an Ethernet MAC. It can be configured through a register interface that is based on I2C (but not I2C protocol compliant). The built-in PHYs are controlled through this register interface, instead of an MDC/MDIO interface through the CPU MAC.